Dr. Pramod Kumar Tiwari

Reasearch Interests

Semiconductor Devices and Circuits

Qualifications

Ph.D. (2012) in Electronics Engineering at Indian Institute of Technology (BHU) Varanasi, UP, India

Teaching/Research Experience

05/12/2019 - Till Date, Associate Professor, Electrical Engineering, IIT Patna , Bihar

18/01/2016 - 04/12/2019, Assistant Professor, Electrical Engineering, IIT Patna , Bihar

26/07/2011 - 15/1/2016, Assistant Professor, Electronics & Communication Engineering, NIT Rourkela, Odisha.

Courses Taught

Undergraduate

  1. Basic Electronics
  2. Semiconductor Devices & Circuits
  3. Analog Communication
  4. Analog Integrated Circuits
  5. Fundamentals of Communication
  6. Electrical Sceinces
  7. Basic Electronics Laboratory
  8. Analog Electronics Laboratory

Postgraduate

  1. Low-power VLSI Circuits
  2. VLSI Technology
  3. MOS Modeling & Simulations
  4. Device Simulation Laboratory

Invited Talks/Guest Lectures

  1. Modern communication from analog to 4G and beyond, NIT Rourkela, 2012
  2. VLSI design and CAD tools, NIT Rourkela, 2013
  3. Invited Talk at GBPEC, Pauri Garhwal Uttarakhad, April 2-3,2017,2017
  4. AICTE Sponsored Short Term Course on Modeling and Simulation of Advanced Semiconductor Devices, IIT (BHU) July 17-22, 2017
  5. Recent Trends in Electronic Devices and Signal processing” October 10th & 11th, 2017 GBPEC, Pauri Garhwal Uttarakhad, 2017
  6. A short term course on "Modeling and Simulation of Advanced Semiconductor Devices & VLSI Circuits" from 07/05/2018 to 11/05/2018, at GBPEC, Pauri Garhwal Uttarakhad, 2017
  7. Faculty Development Program on "Emerging Issues in VLSI Design" from 07/05/2018 to 11/05/2018, at DoECE, SMVD University Katra
  8. Med Tech Innovation, Electronics Circuits and system and their applications in medical electronics, Dec 24, 2018, at IIT Patna
  9. MOSFET Modeling and Simulations (MMS-2018), IIT Patna July 6-8, 2018
  10. Induction program at IIT Patna " Incubation Center" 2019
  11. Workshop for perspective Incubates to Bihar Udyog Vibhag on " Role of Incubation Center" 2019
  12. Drain Current Modeling in 3D MOS Devices, JIIT Noida, 15/2/2019
  13. Junctionless FETs, at Parla Maharaj Engineering College (PMEC),Berhampur, Orrisa 27/2/2019
  14. Mathmetical Modeling of Advanced Semiconductor Devices, at PEC,Jammu, May 4, 2020
  15. Self-heating induced performance Degradation on Nano Scale FETs: an emeregent issue , at Ram Manohar Lohia Avadh University, U.P. 1/7/2020
  16. Self-heating in Nano Scale FETs (Webinar), at GBPEC Pauri, Uttarakhand, 26/8/2020
  17. Self-heating in Nano Scale FETs (Webinar), at NIT Calicut, Kerla, 27/8/2020
  18. Introduction to Incubation Center(Webinar), at IIT Patna, , 19/11/2020
  19. How to pitch an idea for incubation support, Interaction with the students of BIT Mesra, Deoghar Campus, 30/1/2021
  20. Self Heating an emergent issue in nano scale devices, NIT Patna, 27/1/2021
  21. Self Heating in III-IV Devices, NIT Meghalya, 27/1/2021
  22. Self Heating III-IV Devices,GEC Raipur, 2/3/2021
  23. InGaAs MOSFETs for RF applications, NIT Hamirpur, 4/6/2021
  24. Semiconductor Device Simulations, KNIT Sultanpur, 27/7/2021
  25. Modeling of NW MOSFETs including the effect of inclined side-walls, IIIT Bhagalpur, 14/12/2021
  26. Self Heating in nanowire MOSFETs, NIT Warangal, 16/2/2022
  27. Self Heating based Performance Degradaion in InGaAS NW MOSFETs, IEEE, WDC Goa, 24/3/2022

Short-term courses organized

  1. MOSFET Modeling and Simulations (MMS) from July 7, 2018 to July 9, 2018
  2. Helth Techonology Innovation, Incubation Center IIT Patna, Dec 24-28, 2018
  3. Helth Techonology Innovation, Incubation Center IIT Patna, Dec 20-24, 2019 (Sponsered)
  4. Enterpenurship Development Program,Incubation Center IIT Patna, Jan 20-25, 2020 (Sponsered)
  5. Electronics System Development & Manufacuring: Product development, Incubation Center IIT Patna, Fab 6-13, 2020 (Sponsered)
  6. Electronics System Development & Manufacuring: Product development, Incubation Center IIT Patna, Fab 25-March 3, 2020 (Sponsered)
  7. Enterpenurship Development Program,Incubation Center IIT Patna, Fab 25-March 3, 2020 (Sponsered)
  8. 3D Printing 1 Day Training, IIT Patna Jan 30, 2022
  9. IOT with AI & Data Sciences, March 11-March 16, 2022 (Sponsered)
  10. 3D Printing and Design, IIT Patna, June 1-5, 2022

Administrative Responsibilities

  1. Memebr, Senate,IIT Patna, Since March 8, 2022
  2. Convener, Startups and Entrepreneurship Activities, TIH,IIT Patna, Since Aug 2021
  3. Member, DPR Committee, Technology Innovation Hub Project, IIT Patna
  4. Professor in Charge , Incubation Center, IIT Patna 1/12/2017- 20/7/2021
  5. Nodal Officer, Bihar Statrtup Policy, BUV, 1/12/2017- 20/7/2021
  6. PIC, Communication, 1/7/2017 to 1/12/2017
  7. Faculty Advisor of M.Tech 2018 Batch
  8. Member of Institute Registration Committee, 1/12/2016 to 1/12/2017
  9. Departmental Representative to Computer Centre
  10. Faculty Advisor of B.Tech 2016 Batch
  11. PIC, Research Scholar Day 2017
  12. Member of Department Purchase Committee, for 2 Years
  13. Secretary, DAPC, Electrical Engineering till Jan, 2018 (for 1 Year)
  14. Attended Board of Studies meeting of GB Pant Engg College, Pauri Garhwal, an autonomous institute of Uttarakhand Gov
  15. IIT Patna representative of syllabus review committee of Aryabhata Knowledge University, Patna, Bihar
  16. Assistant warden, Homi Bhabha Hall, NIT Rourkela from 2013-2015
  17. Member, APOC, NIT Rourkela, 2015
  18. NBA Acredation responsibility, VLSI & ES, NIT Rourkela
  19. Faculty Advisor, B.Tech 2012 Batch, ECE, NIT Rourkela
  20. PIC, Direct Purchase, ECE, NIT Rourkela 2015-2016

Honours & Awards

  1. Seceratery, IC IIT Patna Soceity Dec 2017- July 2021
  2. Name appeared in Golden list of Reviwers published by IEEE TED and EDL
  3. Senior Member IEEE and IEEE EDS
  4. Life Member Indian Society of Technical Education (ISTE)
  5. Young Scientist Research Grant
  6. UGC Senior Research Fellow
  7. Awarded Travel Grant from Department of Science and Technology
  8. Served as a reviewer for: IEEE EDL, TED, T Nano, IET-CDS, IEEE Sensor J, Super lattices and Microstructure journal, Microelectronics reliability,SSE,JAP, CAP,JCEL, IET Journals,JEM etc

Contribution as PIC Incubation Center

  1. Restructuring of the IC IITP Society
  2. Transition of IC accounting from R&D to IC
  3. DST Recognition for IC
  4. Preparation of Legal agreements for use of IC
  5. Construction of IC permanent facility
  6. Projects Secured for Incubation Center: Nidhi Prayas (6Cr) (DST), Support for Entrepreneurial and Managerial Development of MSMEs through Incubators (15 Lakhs)(MSME
  7. Agreements with AIIMS Patna for medical product trial

Projects

S.no Funding agency Title Cost Duration Role
1 DST Modeling, simulation and performance optimization of Re-S/D SOI MOSFET 22.90 lakhs

(2013-2016)

PI
2 DRDO Analytical investigation of subthreshold behavior of SiNT FETs 19.98 lakhs

(2016-2019)

PI

PI
3 MSME Capacity building training program under MSME National SC ST Hub 15.61 lakhs

(2019-20)

PI
4 IIT Patna Incubation Center Project 4710 lakhs

(2017-2021)

PI

PI
5 MSME Support for Entrepreneurial and Managerial Development of MSMEs through Incubators 15 lakhs

2020-2021

PI
6 GITA/DST Modeling, Simulation and Fabrication of Novel GAA FETs 38.33 Lakhs

Ongoing

(2021-Till Date)

PI
7 DST Design and Development of Silicon Artificial Neuron and Synapse for Brain-Inspired Computing Architectures 33 Lakhs

Ongoing

(2022-Till Date)

Co-PI

Ph.D students

S.no Student Name Title Status Role Current Affiliation
1 Gopi Krishna Saramekala

Modeling, simulation and performance optimization of recessed- source/drain Re-S/D SOI MOSFETs

Completed

(2012-2017)
Supervisor

Assistant Prof., NIT Calicut

2 Visweswara Rao Samoju Modeling and simulation of Dual-metal Quadruple Gate MOSFETs

Completed

(2013-2021)
Co-Supervisor

Senior Member Technical Staff at Maven Silicon

3 Arun Kumar Modeling, simulation and self-heating induced performance degradation analysis of DGAA MOSFETs

Completed

(2016-2020)
Supervisor

Assistant Prof., TIET Patiala

4 Deepti Gola Modeling and simulation of tri-gate (TG) JLFETs with substrate bias effects

Completed

(2016-2020)
Supervisor

Assistant Prof. BIT Mesra

5 P SURYA TEJA NAGA SRINIVAS DC & AC Performance Degradation in III-IV GAA MOSFETs due to Self-Heating

Ongoing

(Since Jan,2018)
Supervisor

....

6 Tripti Kumari Modeling and Simulation of GAA MOSFETs

Ongoing

(Since July,2018)
Joint Supervisor

....

7 Asraf Maniyar Semiconductor Devices

Ongoing

(Since July, 2020)
Supervisor

....

8 Sai Shirova Katta Semiconductor Devices

Ongoing

(Since Jan, 2021)
Supervisor

....

9 Subir Das Semiconductor Devices

Ongoing

(Since Jan, 2021)
Supervisor

....

M.Tech students

S.no Student Name Year of Completion Title Status
1 Abirmoya Santra 2013 Subthreshold modeling of TM DG MOSFETs

Circuit design engineer at Sankalp Semiconductor

partime Ph.D at IIT Madras
2 Shiv Bhushan 2013 Threshold voltage modeling of strained MOSFETs Enrolled for Ph.D program at IIT Patna
3 Santunu Sarangi 2013 Simulation based study of gate misalignment effects in gate engineered DG MOSFETs Enrolled for Ph.D program at IIT kharagpur
4 Shara Mathew 2014 Atlas based simulation study of junction less double gate (DG) tunnel FET Enrolled for Ph.D program at NIT Surathkal
5 Shilpika Mehandi 2014 Performance analysis of dual material gate (dmg) silicon on insulator (soi) tunnel fets Enrolled for Ph.D program at North Eastern Hill University,Shillong
6 Gokula Raju 2014 ATLAS simulation based characterization of Recessed-S/D FD SOI MOSFETs with non-uniform lateral doping
7 Ajit Kumar 2014 Modeling and simulation of subthreshold characteristics of fully-depleted recessed-source/drain UTB SOI MOSFETs including substrate induced surface potential effects Enrolled for Ph.D program at IIT kharagpur
8 Anand Mukhopadhaya 2014 Two-dimensional(2D) subthreshold current and subthreshold swing modeling of double-material-gate(DMG) strained-Si(s-Si) on silicon-germanium(SiGe) MOSFETs. Enrolled for Ph.D program at IIT kharagpur
9 Santosh Kumar Padhy 2015 Atlas simulation of MSM photo detector
10 Mukesh Kumar 2015 A simulation based RF performance study of a Silicon nanotube FET analysis System Engineer at IBM India Pvt Ltd
11 Mukesh Kushwaha 2015 Threshold Voltage Modeling of Recessed- Source/drain Soi Mosfets with Vertical Gaussian Doping Profile
12 Srikanya Dasari 2015 Virtual fabrication of short-channel Recessed-Source/Drain (Re-S/D) SOI MOSFETs Assistant professor at Vignan's Institute of Information Technology (VIIT)
13 Petla Ravi Chandra 2016 Analyzing the electrical characteristics of Junction less optically gated tunnel FET
14 Dipankar Talukdar 2016 Modeling and simulation of gate tunneling current of Re-S/D SOI MOSFET Design Engineer at Si2chip
15 Sradhanjali Mohapatra 2016 Investigation of subthreshold characteristics of vertically doped Gaussian profile Re-S/D SOI MOSFET Scientist-C at ISRO Satellite Centre (ISAC)
16 Kiranmayi Prasada 2016 Modeling and simulation of Re-S/D SOI MOSFET using evanescent method Research staff at BEL
17 Abhilas Srivastava 2019 Digital Sine Wave Generator ST Microelectronics
18 Uday Maurya 2020 FD SOI MOSFETs based converter design ST Microelectronics
19 Abhigyan Dey 2021 Low Resolution High ENOB Nyquist Rate DAC Design Cadance Design System

Selected Research Publications

Selected Book Chapter

  1. Pramod Kumar Tiwari, Sarvesh Dubey and S. Jit, Double-Gate (DG) MOSFETs: A Review, Advances in Microelectronics and Photonics, Nova Science Publishers, USA, 2012(ISBN: 978-1-61470-956-5).
  2. Arun Kumar, and Pramod Kumar Tiwari, Silicon Nanotube FETs: From device concept to analytical model development, Cutting-Edge Research on Low-Dimensional Nanoelectronic Devices: Physics and Material Science Aspects, Apple Academic Press, USA, In production (ISBN: 9781774638668).
  3. Selected International Journals

  4. Ajit Kumar, Pramod Kumar Tiwari, J. N. Roy, “Subthreshold model of asymmetric GAA junctionless FETs with scaled equivalent oxide thickness”, Microelectronics Journal, vol 126, issue 8, pp.105490 (7), 2022.
  5. P. S. T. N. Srinivas, and Pramod Kumar Tiwari, Impact of Self-Heating on Linearity Performance of In0.53Ga0.47As based gate-all-around MOSFETs, IEEE Transactions on Device and Materials Reliability, vol. 22, pp. 42-49, 2022
  6. Tripty Kumari, Pramod Kumar Tiwari, Jawar Singh, and Kuei-Shu Chang Liao, Subthreshold Modeling of GAA MOSFET including the Effect of Process-Induced Inclined Sidewalls, IEEE Transactions on Electron Devices, vol. 69, pp. 487-494, 2022
  7. P. S. T. N. Srinivas, Arun Kumar, and Pramod Kumar Tiwari, Effect of Self-Heating on Small-Signal Parameters of In0.53Ga0.47As Based Gate-All-Around MOSFETs, Semiconductor Science and Technology (SST), vol. 36, pp. 125012(9) , Dec. 2021
  8. Tripti Kumari, Jawar Singh, and Pramod Kumar Tiwari, “Investigation of Ring-TFET for Better Electrostatics Control and Suppressed Ambipolarity", IEEE Transaction on Nanotechnology, vol. 19, pp. 829-836, 2020
  9. Sandeep Moparthi, Pramod Kumar Tiwari,Visweswara Rao Samoju,and Gopi Krishna Saramekala “Investigation of Temperature and Source/Drain Overlap Impact on Negative Capacitance Silicon Nanotube FET (NC Si NTFET) with Sub-60mV/decade Switching", IEEE Transaction on Nanotechnology, vol. 19, pp. 800-806, 2020
  10. Sandeep Kumar,Yashvir Singh, Balraj Singh, and Pramod Kumar Tiwari, “Simulation Study for Dielectric Modulated Dual Channel Trench Gate TFET Based Biosensor", IEEE Sensors Journal, vol. 20, pp. 12565-12573, Nov. 2020
  11. P. S. T. N. Srinivas, Arun Kumar, S.Jit, and Pramod Kumar Tiwari, “Self-heating effects and hot carrier degradation in In0.53Ga0.47As Gate-All-Around (GAA) MOSFETs", Semiconductor Science and Technology (SST), vol. 35, pp. 065008-15, March. 2020
  12. Deepti Gola, Balraj Singh, and Pramod Kumar Tiwari, “Thermal Noise Models for Trigate Junctionless Transistors Including Substrate Bias Effects, IEEE Transactions on Electron Devices, vol. 67, pp. 263-269, Jan. 2020
  13. Arun Kumar, P.S.T.N. Srinivas, and Pramod Kumar Tiwari , “An Insight into Self-heating Effects and its Implications on Hot Carrier Degradation for Silicon-Nanotube-based double gate-all-around (DGAA) MOSFETs", IEEE Journal of Electron Devices Society, vol. 7, pp. 1100-1108, Nov. 2019
  14. Deepti Gola, Balraj Singh, Jawar Singh, Satyabrata Jit, and Pramod Kumar Tiwari, "Static and Quasi-Static Drain Current Modeling of Tri-Gate Junctionless Transistor with Substrate Bias Induced Effects", IEEE Transactions on Electron Devices , Volume: 66 , pp: 2876 – 2883, 2019
  15. Subhradeep Pal, Pramod Kumar Tiwari, and Sumanta Gupta, "An Electrostatic Doping Assisted Silicon Electro-Absorption Modulator For Intra-Chip Communications", IEEE Transactions on Electron Devices , Vol: 66 , no: 5 , pp: 2269-2275, 2019
  16. Deepti Gola, Balraj Singh, Pramod Kumar Tiwari, "Subthreshold Characteristic Analysis and Models for Tri-Gate SOI MOSFETs using Substrate Bias Induced Effects", IEEE Transactions on Nanotechnology , Vol: 18 , no: 3 , pp: 329-335, 2019
  17. Arun Kumar, and Pramod Kumar Tiwari, "Drain current modeling of double gate-all-around (DGAA) MOSFETs", IET-Circuits Devices and Systems (Previously IEE-CDS) , Vol: 13, pp: 519-525, 2019
  18. Arun Kumar, and Pramod Kumar Tiwari, "An Explicit Unified Drain Current Model for Silicon-Nanotube-Based Ultra-thin Double Gate-All-Around (DGAA) MOSFETs", IEEE Transactions on Nanotechnology , vol 17, no 6, pp:1224-34, 2018.(IF=2.8)
  19. Deepti Gola, Balraj Singh and Pramod Kumar Tiwari, "Subthreshold Modeling of Tri-Gate Junctionless Transistors With Variable Channel Edges and Substrate Bias Effects", IEEE Transactions on Electron Devices, Vol. 65, no.5, pp.1663 - 1671, MAY 2018.
  20. Deepti Gola, Balraj Singh and Pramod Kumar Tiwari, "A Threshold Voltage Model of Tri-Gate Junctionless Field-Effect Transistors Including Substrate Bias Effects", IEEE Transactions on Electron Devices, Volume: 64, Issue:9,pp. 3534 – 3540, 2017. (IF=2.605, h5 index 80)
  21. Arun Kumar, Shiv Bhushan, and Pramod Kumar Tiwari, "Threshold voltage modeling of ultra-short Double-gate–all-arround MOSFETs considering quantum confinement effects", IEEE Transaction on NanoTechnology, Volume: 16, Issue: 5, pp. 868 – 875, 2017. (IF=2.485, h5 index 34)
  22. Ajit Kumar, Pramod Kumar Tiwari, “A threshold voltage modeling of Re-S/D SOI MOSFETs including SISP effects”, Solid State Electronics, vol 95, issue 5, pp.52-60, 2014. (SCI , Impact factor :1.345)
  23. Sarvesh Dubey, Abirmoya Santra, Gopi Krishna S., Mirgender Kumar, Pramod Kumar Tiwari, An analytical threshold voltage model for triple-material gate-all-around (TM-GAA) MOSFETs, IEEE Transactions on Nanotechnology, vol 12, no5, pp: 766-773,2013. (SCI , Impact factor :2.47)
  24. Mirgender Kumar, Sarvesh Dubey, Pramod Kumar Tiwari, S. Jit, “Analytical Modeling and Simulation of Subthreshold Characteristics of Back-Gated SSGOI and SSOI MOSFETs: A Comparative Study”, Current Applied Physics, vol.13, pp.1778-1786, 2013. (SCI , Impact factor :2.144)
  25. Sarvesh Dubey, Pramod Kumar Tiwari and S. Jit, “A short-channel subthreshold current and subthreshold swing model for Double-Gate (DG) MOSFETs with a vertical Gaussian-Like Doping Profile”, Journal of Applied Physics, 109, 054508(7), 2011. (SCI , Impact factor :2.185)
  26. Pramod Kumar Tiwari, S. Dubey, M. Singh and S. Jit, “A two-dimensional analytical model for threshold voltage of short-channel triple-material double gate (TM-DG) MOSFETs”, Journal of Applied Physics , 108, pp.074508, 2010. (SCI , Impact factor: 2.185)
  27. Sarvesh Dubey, Pramod Kumar Tiwari and S. Jit, “A 2D Model for the Potential Distribution and Threshold Voltage of Short-Channel Double-Gate (DG) MOSFETs with a Vertical Gaussian-Like Doping Profile”, Journal of Applied Physics, 108, (3), pp.034518 (7), 2010. (SCI , Impact factor :2.185)
  28. Pramod Kumar Tiwari, C. R. Panda, P. Sharma, A. Agrawal and S.Jit, “Doping Dependent subthreshold swing model for DG MOSFETs”, IET-Circuits Devices and Systems (Previously IEE-CDS), Vol.4, No.4, pp.337-345, 2010. (SCI , Impact factor :0.91)
  29. S. Jit, P. K. Pandey, and Pramod Kumar Tiwari, “Modeling of the subthreshold current and subthreshold swing of fully depleted short-channel Si-SOI-MESFETs”, Solid-State Electronics., vol. 53, pp. 57-62, 2009. (SCI , Impact factor :1.514)
  30. Other Journal Publications

  31. Binay Binod Kumar, Pramod Kumar Tiwari, Sarvesh Dubey, Kunal Singh, "Design and investigation of ZnO based thin film transistors for high-speed AMLCD pixel circuit applications", Supperlattice and Microstructure Journal , Vol 164, issue 4, pp.107122 (11), 2022
  32. Yograj Singh Duksh, Balraj Singh, Deepti Gola , Pramod Kumar Tiwari, “Self-heating and Negative Differential Conductance Improvement by Substrate Bias Voltage in Tri-gate Junctionless Transistor", Silicon , vol. XX, pp XX-XX, 2021
  33. Yograj Singh Duksh, Balraj Singh, Deepti Gola , Pramod Kumar Tiwari, S.Jit, “Subthreshold Modeling of Graded Channel Double Gate Junctionless FETs", Silicon , vol. 31, pp. 1231-1238, 2021
  34. Vaibhav Purwar, Rajeev Gupta, Nitish Kumar, Himanshi Awasthi, Vijay Kumar Dixit, Kunal Singh, Sarvesh Dubey, Pramod Kumar Tiwari, “Investigating linearity and efect of temperature variation on analog/ RF performance of dielectric pocket high-k double gate-all-around (DP-DGAA) MOSFETs", Applied Physics A , vol. 126, pp. 746, 2020
  35. Sandeep Moparthi, K.P. Adarsh, Pramod Kumar Tiwari, and Gopi Krishna Saramekala, “Analog and RF performance evaluation of negative capacitance SOI junctionless transistor", AEU - International Journal of Electronics and Communications, vol. 122, pp. 153243, May. 2020
  36. L Ramesh ,S Moparthi , Pramod Kumar Tiwari, V.R. Samoju, G.K. Saramekala , “Investigation of the Electrical Properties of Double-Gate Dual-Active-Layer (DG-DAL) Thin-Film Transistor (TFT) with HfO2/La2O3/HfO2 (HLH) Sandwich Gate Dielectrics", Физика и техника полупроводников (Semiconductors) , vol. 54, pp. 1098, 2020
  37. M. Kumar, S. Singh, Pramod Kumar Tiwari, S.H. Park, “Simulation and Fabrication of Ag/ZnO- Nanorods/Ag Ultraviolet Detectors on p-type Silicon", Digest Journal of Nanomaterials and Biostructures , vol. 15, pp. 75-83, March. 2020
  38. P. S. T. N. Srinivas, Arun Kumar, Pramod Kumar Tiwari, “Threshold Voltage Modeling of tri-Gate Schottky-Barrier (TGSB) Field-Effect-Transistors (FETs)", Silicon , vol. 13, pp. 25-35, 2021
  39. Kunal Singh, S. Kumar, and Pramod Kumar Tiwari, A.B. Yadav, S. Dubey, and S. Jit, "Semianalytical Threshold Voltage Model of a Double-Gate Nanoscale RingFET for Terahertz Applications in Radiation Hardened (Rad-Hard) Environments", Journal of Electronics Material , vol. 48, pp.6366-6371, 2019 DOI:10.1007/s11664-019-07411-3
  40. Arun Kumar, P. S. T. N. Srinivas, Shiv Bhushan, Sarvesh Dubey, Yatendra Kumar Singh, and Pramod Kumar Tiwari, "Threshold Voltage Modeling of Double Gate-All-Around Metal-Oxide-Semiconductor Field-Effect-Transistors (DGAA MOSFETs) Including the Fringing Field Effects", Journal of Nanoelectronics and Optoelectronics , Vol. 14, pp. 1–10, 2019
  41. Visweswara Rao Samoju, Kamalakanta Mahapatra, Pramod Kumar Tiwari, "Analytical modeling of subthreshold characteristics by considering quantum confinement effects in ultrathin dual-metal quadruple gate (DMQG) MOSFETs", Superlattices and Microstructures , Vol. 111, pp. 704-713, 2017. (IF=2.123, h5 index 57)
  42. Shaivalini Singh, Pramod Kumar Tiwari, Hemant Kumar, Yogesh Kumar, Gopal Rawat, Sanjay Kumar, Kunal Singh, Ekta Goel, S. Jit, and Si-Hyun Park, "Theoretical and experimental study of UV detection characteristics of Pd/ZnO nanorod Schottky diodes", NANO: Brief reports and reviews , Volume 12, issue 11, (2017) 1750137 8 pages.
  43. Balraj Singh, Trailokya Nath Rai, Deepti Gola, Kunal Singh, Ekta Goel, Sanjay Kumar, Pramod Kumar Tiwari, Satyabrata Jit, Ferro-electric stacked gate oxide heterojunction electro-statically doped source/drain double-gate tunnel field effect transistors: A superior structure", Materials Science in Semiconductor Processing , Volume 71, issue 11, Pages 161–165, 2017 (IF=2.359, h5 index 31)
  44. A. Kumar., Shiv Bhushan, Pramod Kumar Tiwari, "Analytical modeling of subthreshold characteristics of ultra-thin double gateall-around (DGAA) MOSFETs incorporating quantum confinement effects", Superlattices and Microstructures, Vol. 109, pp. 567-578, 2017. (IF=2.123, h5 index 57)
  45. Gopi krishna Saramekala, Pramod Kumar Tiwari, "Analytical subthreshold current and subthreshold swing models for a fully-depleted (FD) recessed-source/drain (Re-S/D) SOI MOSFET with back-gate control" TMS Journal of Electronic Materials , Vol.46, No. 8, pp-5046-5056, 2017 (SCI, Impact factor: 1.579) h5 index: 34
  46. Visweswara Rao Samoju, Sradhanjali Mohapatra, Shiv Bhushan, and Pramod Kumar Tiwari, "Analytical Modeling and Simulation of Subthreshold Characteristics of RecessedSource/Drain (Re-S/D) Silicon-on-Insulator MOSFETs with Gaussian Doping Profile, Journal of Nanoelectronics and Optoelectronics , Vol. 12, No 5., pp. 490-498, 2017. (SCI, Impact factor: 0.591) h5 index: 17
  47. Gopi krishna Saramekala, Pramod Kumar Tiwari,“An Analytical threshold voltage model for a fully-depleted (FD) recessed-source/drain (Re-S/D) SOI MOSFET with back-gate control”, TMS Journal of Electronic Materials , vol.45, pp. 5367, 2016. (SCI, Impact factor: 1.491) h5 index: 32
  48. Pramod Kumar Tiwari, Visweswara Rao Samoju, Thandva Sunkara, Sarvesh Dubey, Satyabrata Jit, “Analytical Modeling of Threshold Voltage for Symmetrical Silicon Nano-Tube Field-Effect-Transistors (Si-NT FETs)”, Journal of Computaional Electronics , Vol. 15, no. 2, pp 516-524, 2016. (SCI, Impact factor: 1.104)
  49. Pramod Kumar Tiwari, Mukesh Kumar, R Shakru Naik, Gopi krishna Saramekala, “Analog and RF performance study of SiNT MOSFETs”, Journal of Semiconductors , Vol. 37, pp. 064003(1-4), 2016.
  50. Pramod Kumar Tiwari, Visweswara Rao Samoju, Tuhinanshu Gaurav, “A doping dependent subthreshold swing modeling of QG MOSFETs”, Journal of Nanoengineering and Nanomanufacturing , Vol. 5, pp. 1-6, 2015. (doi:10.1166/jnan.2015.1244)
  51. Gopi krishna Saramekala, Pramod Kumar Tiwari, “A ballistic subthreshold current model for ultra-short channel recessed-source/ drain (Re-S/D) SOI MOSFETs”, Journal of Nanoengineering and Nanomanufacturing , Vol. 5, pp. 1-5, 2015. (doi:10.1166/jnan.2015.1239)
  52. Visweswara Rao Samoju, Pramod Kumar Tiwari, “Threshold voltage modeling for dual-metal quadruple-gate (DMQG) MOSFETs”, International Journal of Numerical Modelling: Electronic Networks, Devices and Fields , 2015 (doi: 10.1002/jnm.2126). ( SCI, Impact factor: 0.515)
  53. Gopi krishna Saramekala, Sarvesh Dubey, Pramod Kumar Tiwari, “An Analytical threshold voltage model for recessed source drain SOI MOSFETs with high-k dielectric”, Chinese Physics B , vol. 24, pp. 10505, 2015 (SCI, Impact factor: 1.603)
  54. Visweswara Rao Samoju, Sarvesh Dubey, Pramod Kumar Tiwari, “Quasi-3D subthreshold current and subthreshold swing Models of Dual-Metal Quadruple-Gate (DMQG) MOSFETs” Journal of Computaional Electronics , vol: 14 pp :582–592, 2015 (SCI, Impact factor :1.104)
  55. Visweswara Rao Samoju, Satyabrata Jit, Pramod Kumar Tiwari, “A Quasi-3D Threshold Voltage Model for Dual-Metal Quadruple-Gate (DMQG) MOSFETs”, Chinese Physics letter , Vol. 31 (12), pp. 128502,2014. (SCI, Impact factor :0.927)
  56. Gopi krishna Saramekala, Sarvesh Dubey, Pramod Kumar Tiwari, “ Numerical simulation based study of analog and RF performance of a Re-S/D SOI MOSFETs” Supperlattices and Microstructures Journal , Volume 76, , Pages 77–89, December 2014. (SCI, Impact factor :2.117)
  57. Pramod Kumar Tiwari, Gopi Krishna Saramekala, Annad Mukhopadhaya, Sarvesh Dubey, Analytical subthreshold current and subthreshold swing models for DMG strained-Si MOSFETs, Journal of Semiconductors , vol. 35, no 10, pp. 104002(7), 2014.
  58. Gopi Krishna S., Abirmoya Santra, Pramod Kumar Tiwari, “Analytical subthreshold current and subthreshold swing models for a short-channel dual-metal-gate (DMG) fully depleted recessed-source/drain (Re-S/D) SOI MOSFET’, Journal of Computaional Electronics , vol 13, pp.467-476, 2014. (SCI , Impact factor :1.104)
  59. Abirmoya Santra, Mirgender Kumar, Sarvesh Dubey, Satyabrata Jit, Pramod Kumar Tiwari, “Analytical modeling of threshold voltage of stacked Triple-Material-Gate (TMG) Strained-Si (s-Si) on Silicon-Germanium-on-Insulator (SGOI) MOSFETs”, Journal of Active and Passive Electron Devices , Vol. 9, pp. 235-257, 2014.
  60. Gopi Krishna S., Abirmoya Santra, Sarvesh Dubey, Satyabrata Jit, Pramod Kumar Tiwari, “An analytical threshold voltage model for a short-channel dual-metal-gate (DMG) recessed- source/drain (Re-S/D) SOI MOSFET”, Supperlattices and Microstructures Journal , vol-60,issue-8, pp:580-595,2013. (SCI , Impact factor :1.979)
  61. Santunu Sarangi, Shiv Bhushan, Abirmoya Santra, Sarvesh Dubey, Satyabrata Jit and Pramod Kumar Tiwari, A rigorous simulation based study of gate misalignment effects in gate engineered double-gate (DG) MOSFETs, Supperlattices and Microstructures Journal , vol-60, issue8,263-279,2013. (SCI , Impact factor :2.117)
  62. Shiv Bhushan, Santunu Sarangi, Gopi Krishna S., Abirmoya Santra , Sarvesh Dubey, Pramod Kumar Tiwari, “An Analytical Model for the Threshold Voltage of Short-Channel Double-Material-Gate (DMG) MOSFETs with a Strained-Si (s-Si) Channel on Silicon-Germanium (SiGe) Substrates”, IEEK-Journal of Semiconductor Technology Sciences , vol 13, no 4, pp367-380, 2013. (SCI , Impact factor :0.62)
  63. Mrigendra Kumar, Sarvesh Dubey , Pramod Kumar Tiwari , S. Jit , “Two-Dimensional Modeling of Subthreshold Current and Subthreshold Swing of Double-Material-Gate (DMG) Strained-Si (s-Si) on SGOI MOSFETs”, Journal of Computaional Electronics , vol-12, issue 2, pp;275-280, 2013. (SCI , Impact factor :1.104)
  64. Sarvesh Dubey , Mrigendra Kumar, Pramod Kumar Tiwari, S. Jit, “Analytical threshold voltage model for short-channel Strained-Si on Silicon-Germanium-on-Insulator (SGOI) MOSFETs with localized charges”, Journal of Computational and Theoretical Nano. Sciences , vol 11, issue 1, pp:1-8, 2014. (SCI , Impact factor :1.104)
  65. Mrigendra Kumar, Sarvesh Dubey, Pramod Kumar Tiwari , S. Jit, “Analytical subthreshold current and subthreshold swing model for Strained-Si on Silicon-Germanium-on-Insulator (SGOI) MOSFETs”, Supperlattice and Microstructure Journal , Vol 58, issue 4, pp.1-10, 2013. (SCI , Impact factor :2.117)
  66. Mrigendra Kumar, Sarvesh Dubey , Pramod Kumar Tiwari, “S. Jit, An analytical model of threshold voltage for short-channel double-material gate strained-Si on Silicon Germenioum on isulator MOSFET”, Journal of Computaional Electronics , vol 12, issue 1, pp 20-28, 2013. (SCI , Impact factor :1.104)
  67. Sarvesh Dubey, Pramod Kumar Tiwari, S. Jit, “On current modeling of Gaussian doped DG MOSFET”, Journal of Semiconductors , vol. 34, no.5, pp 054001(8), 2013.
  68. Shiv Bhushan, Santunu Sarangi, Abirmoya Santra, Mirgender Kumar, Sarvesh Dubey, S. Jit, Pramod Kumar Tiwari, “An analytical surface potential model for s-Si on SiGe MOSFET including the effects of interface charges”, Journal of Electron Devices , vol.15, pp. 1285-1290, 2012. (SCI, Impact factor :0.48)
  69. Pramod Kumar Tiwari, Sarvesh Dubey and S. Jit, “Analytical modeling for the subthreshold current and subthreshold swing of the triple-material double-gate(TM-DG) MOSFETs”, Supperlattice and Microstructure Journal , vol. 51(5), pp. 715-724, 2012. (SCI , Impact factor :1.979)
  70. Pramod Kumar Tiwari and S.Jit, “A 2D Model for Potential Distribution and Threshold Voltage of Double-Gate (DG) MOSFETs with Vertical Gaussian Doping Profile”, Journal of Nan electron. Optoelectron. , vol. 6(2), pp. 207-213(7), 2011. (SCI)
  71. Pramod Kumar Tiwari, Sarvesh Dubey and S.Jit, “Doping dependent threshold voltage model for short-channel double-gate(DG) MOSFETs”, J. Nano- Electron. Phys , . 3 No1, 963, 2011. (SCI , Impact factor :0.256)
  72. Sarvesh Dubey, Dhiraj Gupta, Pramod Kumar Tiwari, and S. Jit, “2D analytical modeling of threshold voltage of doped short-channel triple-material double-gate (TM-DG) MOSFETs”, J. Nano- Electron. Phys. 3 No1, 576, 2011. (SCI , Impact factor :0.256)
  73. Sarvesh Dubey, Pramod Kumar Tiwari and S. Jit, “A Two-Dimensional Model for the Surface Potential and Subthreshold Current of Doped Double-Gate (DG) MOSFETs with a Vertical Gaussian-Like Doping Profile”, J. Nanoelectron. Optoelectron. , 5, 332-339, 2010. (SCI)
  74. Pramod Kumar Tiwari and S. Jit, “Subthreshold current model for short-channel double-gate (DG) MOSFETs with vertical Gaussian doping profile” Journal of Computational and Theoretical Nano. Sciences , vol. 8(7), pp. 1296-1303, 2011. (SCI , Impact factor :1.03)
  75. Pramod Kumar Tiwari and S.Jit, “A Doping-Dependent Short-Channel Subthreshold Current model for Symmetric Double-Gate (DG) MOSFETs” Journal of Nanoelectronics and Optoelectronics (JNO) ., Vol. 5, No.1, pp. 82-88, 2010. (SCI)
  76. Pramod Kumar Tiwari and S.Jit, “A 2D Model for Potential Distribution and Threshold Voltage of Symmetric Double-Gate (DG) MOSFETs With Vertical Gaussian Doping Profile”, Journal of Electron Devices (France) ,vol.7, pp.241-249, 2010. (SCI , Impact factor :0.48)
  77. Pramod Kumar Tiwari and S.Jit, “A Subthreshold Swing Model for Symmetric Double-Gate (DG) MOSFETs with Vertical Gaussian Doping”, IEEK-Journal of Semiconductor Technology Sciences , Vol.10, N0.2, pp.107- 117, 2010. (SCI , Impact factor :0.62)
  78. Conference Publications

  79. Tripty Kumari, Jawar Singh, Pramod Kumar Tiwari , "Impact of Non-Rectangular Cross-Section on Electrical Performances of GAA FETs" in 2021 IEEE 18th India Council International Conference (INDICON), Guwahati, India, Dec 2021.
  80. Sandeep Moparthi, Pramod Kumar Tiwari , and Gopi Krishna Saramekala, "Genetic algorithm-based threshold voltage prediction of SOI JLT using multi-variable nonlinear regression" in International Symposium on Devices, Circuits and Systems (ISDCS), Higashihiroshima, Japan, March 2021.
  81. Sandeep Moparthi, Chandan Yadav, Gopi Krishna Saramekala, and Pramod Kumar Tiwari, "Machine Learning Based Device Simulation Using Multi-variable Non-linear Regression to Assess the Impact of Device Parameter Variability on Threshold Voltage of Double Gate-All-Around (DGAA) MOSFET" IEEE International Conference on Circuits and Systems (ICCS), Chengdu, China Dec 2020
  82. Arun Kumar, P.S.T.N. Srinivas, and Pramod Kumar Tiwari , “Analytical Modeling of Subthreshold Current and Subthreshold Swing of Schottky-Barrier Source/Drain Double Gate-All-Around (DGAA) MOSFETs,” in 5th IEEE International Symposium on Smart Electronic Systems, Rourkela, Dec. 2019.
  83. Deepti Gola, Balraj Singh, and Pramod Kumar Tiwari , "Analytical Modeling of Analog/RF Parameters for Trigate Junctionless Field Effect Transistor Incorporating Substrate Biasing Effects”, accepted in Proc. IEEE TENCON 2019, 17-20th Oct. 2019.
  84. A. Kumar, P.S.T.N. Srinivas, and Pramod Kumar Tiwari, “Compact Drain Current Model for Ultra-thin Double Gate-All-Around (DGAA) MOSFETs Incorporating Short Channel Effects," IEEE NMDC, Stockholm Oct. 2019.
  85. A. Kumar, P.S.T.N. Srinivas, and Pramod Kumar Tiwari, “Analytical Modeling of Subthreshold Characteristics of Silicon-Nanotube-based Double Gate-All-Around (DGAA) FETs Incorporating Fringing Field Effects," IEEE NMDC, Stockholm Oct. 2019.
  86. A. Kumar, P.S.T.N. Srinivas, and Pramod Kumar Tiwari, “Physical Insight into Self-heating Effects in Ultra-thin Junctionless Gate-All-Around FETs," IEEE INEC, Kuching, July 2019.
  87. A. Kumar, P.S.T.N. Srinivas, and Pramod Kumar Tiwari, “Effects of Lateral Spreading in 2-Dimensional Non-Uniform Doped Junctionless FinFETs," IEEE INEC, Kuching, July 2019.
  88. A. Kumar, P.S.T.N. Srinivas, and Pramod Kumar Tiwari, "Analytical Threshold Voltage Model of Schottky-source/drain (Schottky-S/D) double gate-all-around (DGAA) Field-Effect- Transistors", Devices for Integrated Circuit (DevIC), Kalyani, March 2019
  89. Subhradeep Pal, Pramod Kumar Tiwari, and Sumanta Gupta, "Novel optical modulator using junction-less metal gate MOS phase shifter on SOI platform", 2017 4th International Conference on Opto-Electronics and Applied Optics, 2017
  90. S. Bhushan, A. Kumar, D. Gola, and Pramod Kumar Tiwari, "An analytical subthreshold current model of short-channel symmetrical double gate-all-around (DGAA) field-effect-transistors", Devices for Integrated Circuit (DevIC), Kalyani, March 2017 Devices for Integrated Circuit (DevIC), Kalyani, 2017, pp. 211-215.
  91. Pramod Kumar Tiwari, Arun Kumar and Dipankar Talukdar, An analytical gate tunneling current model of Re- S/D SOI MOSFETs, IEEE UPCON-2016, IIT BHU.
  92. Mukesh Kushwaha, Gopi Krishna Saramekala, and Pramod Kumar Tiwari “Threshold Voltage Modeling of Recessed- Source/drain Soi Mosfets with Vertical Gaussian Doping Profile” International conference on materials for advance material research society of Singapore, suntech city, 2015.
  93. Srikanya Dasari, Gopi krishna Saramekala and Pramod Kumar Tiwari “virtual fabrication of short channel Recessed-Source Drain (Re-S/D) SOI MOSFETs” Third international symposium on semiconductor materials and devices, Anna university, Tamilnadu, 2015
  94. Sarvesh Dubey, Anand Mukhopadhyay, Mirgender Kumar and Pramod Kumar Tiwari, “Effect of Temperature Variation on the Characteristics of Dual-Metal Gate Strained Silicon on Si1-XGeX Substrate MOSFET”, Third international symposium on semiconductor materials and devices, Anna university, Tamilnadu, 2015
  95. Gopi Krishna Saramekala, Pramod Kumar Tiwari, “Analytical subthreshold current modeling of Re-S/D SOI MOSFETs with high K dielectric”, IEEE Asia Modeling Symposium 2014, Taiepi, Taiwan, ISBN 978-1-4799-6487-1, pp.258-264
  96. Shara Mathew, Silpeeka Medhi, and Pramod Kumar Tiwari,, “A Performance Analysis of Hetero- Dielectric Dual-Material-Gate Silicon-on-Insulator Tunnel-Field-Effect Transistors (HD-DMG SOI TFETs)”, IEEE India conference INDICON 2014, 11-13 Dec, Yashada, Pune, India
  97. Gopi Krishna S., Abirmoya Santra, Pramod Kumar Tiwari, “An analytical surface potential modeling of dual-metal-gate (DMG) recessed- source/drain (Re-S/D) SOI MOSFET, International Conf. on Advanced Trends in Engineering and Technology”, Dec 19-20, 2013, Jaipur, India, pp.160 to 163
  98. Gopi Krishna Saramekala, Satyabrata Jit, and Pramod Kumar Tiwari, “ATLAS based simulation study of the electrical characteristics of dual-metal-gate (dmg) fully-depleted (fd) recessed-source/drain (RE-S/D) SOI MOSFETS”, IEEE Conference ICAEE-2014, VIT University Vellore, Jan 9-11, 2014.
  99. Santunu Sarangi, Gopi Krishna .S, Abirmoya Santra, Shiv Bhushan, and Pramod Kumar Tiwari, An Analytical Surface Potential Model of a Gate Misaligned Triple-Material Double-Gate (TM DG) MOSFET, ICQNM-2013, Barcelona, Spain
  100. Santunu Sarangi, Gopi Krishna .S, Abirmoya Santra, Shiv Bhushan, and Pramod Kumar Tiwari, “A Simulation-based Study of Gate Misalignment Effects in Triple-Material Double-Gate (TM DG) MOSFETs" IEEE conference proceedings, IMAC4S, Palai, Kerala Mar 2013, pp.41
  101. S. Sarangi, A. Santra, S. Bhushan, Gopi Krishna S., and Pramod Kumar Tiwari, “An Analytical Surface Potential Modeling of Fully-Depleted Symmetrical Double-Gate (DG) Strained-Si MOSFETs Including the Effect of Interface Charges", IEEE conference proceedings, SCES, Allahabad, Mar 2013 pp.1-5.
  102. Mirgender Kumar, Sarvesh Dubey, Pramod Kumar Tiwari, S. Jit, A Comparative Study of Short-Channel-Effects of strained-Si on Insulator (SSOI) and strained-Si on Silicon-Germanium-on-Insulator (SSGOI) MOSFETs, in International Conference on Electrical and Electronics Engineering (ICEEE-2013), accepted for @WCE conference proceeding, London, July 04-06, 2013.
  103. Mirgender Kumar, Sarvesh Dubey, Pramod Kumar Tiwari, and S. Jit, “Back Gated (BG) Strained-Si-on-Silicon-Germanium-on-Insulator (SSGOI) MOSFETs for Improved Switching Speed and Short-Channel-Effects (SCEs)”, in international conference on Recent Trends in Applied Physics and Material Science, accepted for @AIP conference proceeding, Bikaner, Feb 01-03, 2013.
  104. Mirgender Kumar, Sarvesh Dubey, Pramod Kumar Tiwari, and S. Jit, “Quantitative Performance Investigations of Back Gated Strained-Si-on-Insulator (SSOI) MOSFETs: Towards Double-Gate (DG) Operation”, in international conference on Nanoelectronics and Nano devices (ICNEND), accepted for @SNEM conference proceeding, Chennai, Jan. 21-22, 2013.
  105. Santunu Sarangi, Gopi Krishna .S, Abirmoya Santra and Pramod Kumar Tiwari, A Simulation-based Study of Gate Misalignment Effects in Triple-Material Double-Gate (TM DG) MOSFETs, Accepted for oral presentation in International Multi Conference on Automation, Computing, Control, Communication and Compressed Sensing, Kerala, March 22-23, 2013.
  106. Mirgender Kumar, Sarvesh Dubey, Pramod Kumar Tiwari and S.Jit, A 2D Analytical Modeling Approach for Nanoscale Strained-Si (s-Si) on Silicon-Germanium-on-Insulator (SGOI) MOSFETs by Evanescent Mode Analysis, accepted for poster presentation in CODIS-2012, Jadvpur University, Kolkata.
  107. Mirgender Kumar, Sarvesh Dubey, Pramod Kumar Tiwari and S. Jit, An Analytical Modeling of Interface Charge Induced Effects on Subthreshold Current and Subthreshold Swing of strained-Si (s-Si) on Silicon-Germinium-on-Insulator (SGOI) MOSFETs, accepted for oral presentaion in CODEC-12, CU, Kolkata
  108. Mirgender Kumar, Sarvesh Dubey, Abirmoya Santra, Pramod Kumar Tiwari and S. Jit, An Analytical Study of Short-Channel Effects of Strained-Si on Silicon-Germanium-on-Insulator (SGOI) MOSFETs Including Interface Charges, ICQNM-2012, Roma, Italy, Aug 19-24,2012.
  109. Mirgender Kumar, Sarvesh Dubey, Pramod Kumar Tiwari and S. Jit, Extremely Scaled EOT Bi-Layered stacked High-k (BSK) Double-Material Double-Gate (DM DG) Strained-Si (S-Si) Channel MOSFET for High Performance Band-Edge (BE) CMOS Technology, RANET-2011, IIITM Gwalior.
  110. Abirmoya Santra, Sarvesh Dubey, Mirgender Kumar, Pramod Kumar Tiwari and S. Jit, An Analytical Study of Effect of Interface Charges on the Surface Potential of Strained-Si on Silicon-Germanium-on-Insulator (SGOI) MOSFETs, Emerging trend in Electrical and Electronics Engineering,ETEEE-2011, KNIT Sultanpur, U.P. India, pp-56-57
  111. Mirgender Kumar, Sarvesh Dubey, Pramod Kumar Tiwari and S. Jit, ATLASTM Based Simulation Study of Surface Potential of Double-Material-Gate Strained-Si on Silicon-Germanium-on-Insulator (DMG-SGOI) MOSFETs, Accepted for publication in the proceedings of International Conference on Multimedia Signal Processing and communication technologies 2011( IMPACT 2011), Aligarh Muslim University, India.
  112. Harshit Agnihotri, Abhishek Ranjan, Pramod Kumar Tiwari and S.Jit, An Analytical Drain Current Model for Short-Channel Triple-Material Double-Gate MOSFETs, IEEE Computer Society Annual Symposium on VLSI (ISVLSI-2011), 327-328.
  113. Sarvesh Dubey, Pramod Kumar Tiwari, S. Jit, “A Drain Current Model for Short-Channel Doped Double-Gate (DG) MOSFETs with Vertical Gaussian-like Doping Profile”, Accepted in 5th International Conference on Quantum, Nano and Micro Technologies (ICQNM-11), August, France, 2011.
  114. Pramod Kumar Tiwari, Sarvesh Dubey and S.Jit, Doping dependent threshold voltage model for short-channel double-gate(DG) MOSFETs, in International symposium on semiconductor materials and devices -2011, held at M. S. University, Vadodara, India.
  115. Sarvesh Dubey, Dhiraj Gupta, Pramod Kumar Tiwari, and S.Jit, 2D analytical modeling of threshold voltage of doped short-channel triple-material double-gate(TM-DG) MOSFETs , International symposium on semiconductor materials and devices -2011, held at M. S. University, Vadodara, India.
  116. Pramod Kumar Tiwari, Sarvesh Dubey, Manjeet Singh and S. Jit, An Analytical Subthreshold Current Model for Triple Material Double Gate (TMDG) MOSFETs ,in Proc. International Conference on Electronics System- 2011(ISBN: 978-93-80697-50-5), NIT Rourkela, pp.142-145, 2011.
  117. Pramod Kumar Tiwari, Sarvesh Dubey and S.Jit, “ A short-channel subthreshold swing model for asymmetric 3-T DG MOSFETs” in proc. International conference on solid-state and integrated circuit technology (ICSICT-2010), Shanghai, ROC, pp. 1796-1798.
  118. Pramod Kumar Tiwari, Sarvesh Dubey and S.Jit, Subthreshold current model for gaussian doped dG MOSFET, In the proceeding of the Latest Trends on Circuits System and Signal, Greece,2010, pp. 27-34
  119. Pramod Kumar Tiwari, C. R. Panda, A. Agarwal, P. Sharma and S. Jit, "Analytical Modeling of Effective Conduction Path Effect (ECPE) on the Subthreshold Swing of DG-MOSFETs," published in the procd. of Spanish Conference on Electron Devices (CDE),pp. 136-139,2009,available on line at www.ieee.org.
  120. Pramod Kumar Tiwari, Samarth Mittal, Vaibhav Srivastava, Utkarsh Pandey and S. Jit, "A 2D Analytical Model of the Channel Potential and Threshold Voltage of Double-Gate (DG) MOSFETs With Vertical Gaussian Doping Profile," published in the procd of IMPACT-2009, Aligarh, pp.52-55. 2009,
  121. S.Dubey, Pramod Kumar Tiwari and S.Jit," Surface potential model for Gaussian doped DG MOSFET" in proc. IWPSD-2009, J.M.I. New Delhi
  122. S. Maheshwari, Pramod Kumar Tiwari and I. A. Khan, "Fully differential first order all-pass filter circuit," presented at National Conference: MTECS-08, AMU ,2008.

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