Dr. Kailash Chandra Ray

Dr. Kailash Chandra Ray

Associate Professor

Ph.D, IIT Kharagpur

Ph: +91-612-302 8106 (Off.) +91-612-302 8085 (Lab)

Fax: +91-612-227 7383

kcr[*AT]iitp.ac.in

Research Areas VLSI architectural design, VLSI Signal Processing, Digital VLSI Design, Hardware design methodologies, FPGA based System Design, CORDIC
Ph.D. Students
Name of Ph.D. ScholarArea of Research / Ph.D. Thesis TitleStatus
Vikas Kumar
Vikas Kumar
CORDIC-Based Reconfigurable VLSI Architectures for Wireless Communication Systems Completed
K. K. Soundra Pandian
K. K. Soundra Pandian
Efficient Key Generation Algorithm and Architectures for Cryptography Applications Completed
Sandeep Raj
Sandeep Raj
Development and hardware prototype of an efficient method for handheld arrhythmia monitoring device Completed
Amit Kumar Panda
Amit Kumar Panda
Design and implementation of an efficient pseudorandom bit generation method and its VLSI architecture Completed
Rakesh Pallisetty
Rakesh Pallisetty
Design and implementation of low PAPR and variable rate multicarrier baseband architecture Completed
Pritiranjan Khatua
Pritiranjan
VLSI Signal Processing Ongoing
Vivek Singh
Vivek
Secured Processor Design Ongoing
Satyam Shukla
Satyam
Low Power Processor Design Ongoing
Garima Sahu
Garima Sahu
Embedded System and Biomedical Signal Processing Ongoing
Biranchi Narayan Behera
B.N Behera
VLSI for Wireless Communication System Ongoing
Sujeet Kumar
Sujeet Kumar
VLSI for Edge Computing System Ongoing
Professional Experience
  • Associate Professor, Electrical Engineering Department, Indian Institute of Technology Patna since July 2018
  • Assistant Professor, Electrical Engineering Department, Indian Institute of Technology Patna during June 2010 - July 2018
  • Lecturer, Indian Institute of Information Technology, Allahabad, India during Aug 2008-June 2010
  • Design Engineer, CMOS Chips, Bangalore, India during Mar 2001-Feb 2003
Member of Professional bodies IEEE
Current Sponsored projects
TitleChief InvestigatorsSponsored by
Design and FPGA prototyping of multicarrier multiple access schemes for variable rate multimedia satellite communication Dr. Preetam Kumar and Dr. Kailash Chandra Ray
Co-Investigator: Dr. Arijit Mondal
DEIT, Delhi
Design and Implementation of Novel VLSI Architectures of PRNG for Cryptography Applications Dr. Kailash Chandra Ray CSIR, New Delhi
SMDP-C2SD

CI: Dr. Kailash Chandra Ray

Co-CI: Dr. Arijit Mondal

DeitY, Delhi
Teaching
  • VLSI Design (EE310, EE309)
  • Digital VLSI Systems (EE511)
  • Embedded System (EE360)
  • VLSI Lab (EE311)
  • Embedded System Lab (EE361)
  • VLSI Lab (EE515)
  • Embedded System Lab (EE516)
Short Term Course
TitledDuringPrincipal Coordinator
FPGA Based System Design 25th-30th May 2015 Dr. Kailash Chandra Ray
Publications

Patent Granted:

    • Pratik Kumar Parmar, Kailash Chandra Ray, “Automatic Booklet scanning machine and its method of working” Patent No. 358176 (Indian Patent Application No.1082/KOL/2015).

Journal Publications:
  • Rakesh Palisetty, A. K. Panda and K. C. Ray, "ASIC Implementation of Low PAPR Multidevice Variable-Rate Architecture for IEEE 802.11ah”, IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 70, NO. x, PP.1-10, Jan 2021.
  • A. K. Panda, R. Palisetty and K. C. Ray, "High-Speed Area-Efficient VLSI Architecture of Three-Operand Binary Adder", IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 11, pp. 3944-3953, Nov. 2020, doi: 10.1109/TCSI.2020.3016275.
  • A. K. Panda and K. C. Ray, "A Coupled Variable Input LCG Method and Its VLSI Architecture for Pseudorandom Bit Generation", IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 69, NO. 4, PP. 1011-1019, APRIL 2020.
  • R. Palisetty and K. C. Ray, "Multiuser Variable Rate GO-OFDMA Architecture and Its FPGA Prototype," in IEEE Systems Journal, August 2019. DOI : 10.1109/JSYST.2019.2931942.
  • R. Palisetty and K. C. Ray, Oversampled CI-OFDM Baseband Transceiver Architecture and Its FPGA Prototype, IETE Journal of Research (Taylor and Francis), July 2019. DOI: 10.1080/03772063.2019.1634493.
  • A. Agarwal, V. K. Sinha, R. Palisetty, P. Kumar, K. C. Ray, K. Kumar, and T. Pandey, “Performance Analysis and FPGA Prototype of Variable Rate GO-OFDMA Baseband Transmission Scheme, Wireless Personal Communications (Springer), Volume 108, Issue 2, pp 785–809, September 2019.
  • K.C. Ray and A. S. Dhar, "CORDIC-Based VLSI Architectures of Running DFT with Refreshing Mechanism" Journal of Signal Processing Systems (2018).
  • A. K. Panda and K. C. Ray, “Modified Dual-CLCG Method and its VLSI Architecture for Pseudorandom Bit Generation”, IEEE Transactions on Circuits and Systems--I: Regular Papers, Vol. 66, Issue 3, pp. 989-1002, Mar. 2019.
  • Sandeep Raj and K. C. Ray, "A Personalized Point-Of-Care Platform for Real-Time ECG Monitoring", IEEE Transaction on Consumer Electronics, Vol. 64, issue. 4, pp.452-460, Nov. 2018.
  • K. C. Ray, M.V.N.V.Prasad, and A. S. Dhar, "An Efficient VLSI Architecture for Computation of Discrete Fractional Fourier Transform" Journal of Signal Processing Systems, Vol. 90, Issue 11, pp 1569–1580, Nov. 2018.
  • Sandeep Raj, and K. C. Ray, "Automated recognition of cardiac arrhythmias using sparse decomposition over composite dictionary", Comput. Methods Programs Biomed. (Elsevier), vol. 165, Oct. 2018, pp. 175-186.
  • Sandeep Raj, K. C. Ray and O. Shankar, "Development of Robust, Fast and Efficient QRS Detector: A Methodological Review", Australas Phys Eng Sci Med. (Springer), vol. 41, no. 3, Sept. 2018, pp. 581-600.
  • Sandeep Raj and K. C. Ray, "A personalized arrhythmia monitoring platform", Scientific Reports (Nature), vol. 8, no. 11395, Jul. 2018, pp. 1-11.
  • S. Raj, K. C. Ray, "Sparse representation of ECG signals for automated recognition of cardiac arrhythmias", Expert Syst. Appl., vol. 105, Sept. 2018, pp. 49-64.
  • R. Palisetty and K. C. Ray, "FPGA Prototype and Real Time Analysis of Multiuser Variable Rate CI-GO-OFDMA," in IEEE Transactions on Instrumentation and Measurement, vol. 67, no. 3, pp. 538-546, March 2018.
  • Vikas Kumar, K. C. Ray and Preetam Kumar, "A VLSI architecture of CORDIC-based popular windows and its FPGA pr ototype", InternationalJournal of High Performance Systems Architecture (IJHPSA), Vol. 7, No.2, pp.57-69, 2017.
  • Sandeep Raj, K. C. Ray, "ECG Signal Analysis Using DCT-Based DOST and PSO Optimized SVM", IEEE Transactions on Instrumentation and Measurement, Vol. 66, Issue 3, pp. 470-479, Mar. 2017.
  • K. K. Soundra Pandian and K. C. Ray, "An algorithm and architecture for non-recursive pseudorandom sequence generation using sequence folding technique", Int. J. of Computers and Applications, pages 45-56, 39(1), Dec. 2016.
  • K. K. Soundra Pandian and K. C. Ray, "Dynamic Hash key based stream cipher for secure transmission of real time ECG signal", Security and Communication Networks, pages 4391 – 4402 9 (17), Nov. 2016.
  • Sandeep Raj, K. C. Ray and Om Shankar, "Cardiac arrhythmia beat classification using DOST and PSO tuned SVM", Computer Methods and Programs in Biomedicine (Elsevier), Vol. 136, pp. 163-177, Nov. 2016.
  • Piyush Sharma and K. C. Ray, "Efficient methodology for electrocardiogram beat classification", IET Signal Processing, Vol. 10, Issue 7, pp. 825 - 832, Sept. 2016.
  • Sandeep Raj, Kshitij Maurya and K. C. Ray, "A knowledge-based real time embedded platform for arrhythmia beat classification", Biomedical Engineering Letters (Springer), Vol. 5, Issue 4, pp. 271-280, December 2015.
  • K. K. Soundra Pandian and Kailash Chandra Ray, “Non-singular sequence folding-based pseudorandom key generation algorithm for cryptographic processor”, Security and Communication Networks, Vol. 8, Issue 18, pages 4019–4027, Dec. 2015.
  • Sandeep Raj, G.S.S. Praveen Chand and K. C. Ray, "ARM-based arrhythmia beat monitoring system", Microprocessors and Microsystems(Elsevier),Vol. 39, Issue 7, Pages 504–511, Oct. 2015.
  • K. K. Soundra Pandian and K. C. Ray, “Five Decade Evolution of Feedback Shift Register: Algorithms, Architectures and Applications”, Int. J. of Communication Networks and Distributed Systems, Vol.15, No.2/3 pp.279–312, 2015
  • R. Shukla and K. C. Ray, "Low Latency Hybrid CORDIC Algorithm" IEEE TRANSACTIONS ON COMPUTERS, VOL. 63, NO. 12, PP. 3066-3078, DECEMBER 2014.
  • Vikas Kumar, K. C. Ray and Preetam Kumar, "CORDIC-based VLSI architecture for real time implementation of flat top window" Microprocessors and Microsystems (Elsevier), Vol. 38, Issue 8 (Part B), Pages 1063–1071, Nov. 2014.
  • K. C. Ray and A. S. Dhar, "CORDIC-based VLSI Architecture for implementing Kaiser-Bessel window in real time spectral analysis" Journal of Signal Processing Systems (Springer), Vol. 74, Issue 2, pp 235-244, February 2014.
  • K. C. Ray and A. S. Dhar, "High throughput VLSI architecture for Blackman windowing in real time spectral analysis", Journal of Computers, Vol.3, No.5, pp.54-59, May. 2008 
  • K. C. Ray and A. S. Dhar, "CORDIC-based unified VLSI architecture for implementing windowing functions for real time spectral analysis", IEE Proc. Circuits Devices Syst., Vol. 153, No. 6, pp.539-544, Dec. 2006.

Conference Publications:
  • Pritiranjan Khatua and K. C. Ray, " A basis function for DCT based Discrete Orthogonal S-Transform”, 5th IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS), pp.7-11, Rourkela, India, Dec. 16th – 18th, 2019.
  • A. K. Panda, R. Palisetty and K. C. Ray, "Area-Efficient Parallel-Prefix Binary Comparator”, 5th IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS), pp.12-16, Rourkela, India, Dec. 16th – 18th, 2019.
  • Garima Sahu and K. C. Ray, "An efficient Signal Processing Technique for automated Myocardial Infarction Detection”, 5th IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS), pp.93-98, Rourkela, India, Dec. 16th – 18th, 2019.
  • Vivek Singh, K. C. Ray and Somanath Tripathy, "Blind Detection and Classification algorithm for Smart Audio Monitoring System”, 5th IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS), pp.133-138, Rourkela, India, Dec. 16th – 18th, 2019.
  • S. Shukla and K. C. Ray, "Design and ASIC Implementation of a Reconfigurable Fault-Tolerant ALU for Space Applications”, 5th IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS), pp. 156-159, Rourkela, India, Dec. 16th – 18th, 2019.
  • A. K. Panda and K. C. Ray, "Design and FPGA Prototype of 1024- bit Blum-Blum-Shub PRBG Architecture", _IEEE Int. Conf. on Information Communication and Signal Processing (IEEE-ICICSP2018)_, Singapore, pp.38-43. Nov. 2018.
  • R. Palisetty, A. K. Panda and K. C. Ray, "Secure OFDM based on Coupled Linear Congruential Generator and its FPGA Prototype", _IEEE Int. Conf. on Information Communication and Signal Processing (IEEE-ICICSP2018_ ), Singapore, pp. 54-58, Nov.2018.
  • R. Palisetty, K.C. Ray, "Fixed-Point Design of 1024-Point CI-OFDM for DVB-Satellite to Handheld", Lecture Notes in Electrical Engineering: Advances in Communication, Devices and Networking (Springer), vol 462, pp. 485-493, May 2018.
  • S. Raj, K. C. Ray, "Application of variational mode decomposition and ABC optimized DAG-SVM in arrhythmia analysis", 7th Int. Sympo. on Embedded Computing and System Design (ISED-2017), pp. 1-5, 18-20 Dec. 2017.
  • K. K. Soundra Pandian and K. C. Ray, "FPGA Implementation of hash key based stream cipher using NFSR and its security aspects", IEEE Int. Conf. on Computing, Analytics and Security Trends (CAST), pp.1-6, Pune, India, Dec. 19th - 21st 2016.
  • K. C. Ray and A. S. Dhar, “CORDIC-based parallel architecture for one dimensional discrete Mellin transform” 2016 IEEE Region 10 Conference (TENCON), pp. 1638 - 1643, Singapore, Nov. 22nd -25th , 2016 (DOI: 10.1109/TENCON.2016.7848295).
  • Vikas Kumar, K. C. Ray and Preetam Kumar,"Low-complexity CORDIC-based VLSI Design and FPGA Prototype of CI-OFDMA System for Next-generation", 12th IEEE Colloquium on Signal Processing and its Applications (IEEE-CSPA 2016), Malacca, Malaysia, Mar. 2016 (BEST PAPER AWARD).
  • Vikas Kumar, K. C. Ray and Preetam Kumar, "CORDIC-based VLSI architecture for implementing CI-OFDM and its FPGA prototype", Int.  Conf. on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA-2016), pp.1-5, Bengaluru, India, Jan.10-12th, 2016 (DOI:10.1109/VLSI-SATA.2016.7593037).
  • A. K. Panda; K. C. Ray, “ FPGA Prototype of Low Latency BBS PRNG”, IEEE Int., Symposium on Nanoelectronic and Information Systems (IEEE-iNIS 2015), Indore, India, Pages: 118 – 123, Dec. 21-23, 2015. (DOI:10.1109/iNIS.2015.35).
  • A. K. Singh ; M. K. Singh; K. C. Ray, “  Design and Implementation of Quadruple Floating-Point CORDIC”, IEEE Int., Symposium on Nanoelectronic and Information Systems (IEEE-iNIS 2015), Indore, India, Pages: 286 - 290, Dec. 21-23, 2015. (DOI:10.1109/iNIS.2015.23).
  • Sandeep Raj, Sunny Luthra and Kailash Chandra Ray, “Development of Handheld Cardiac Event Monitoring System”, 13th IFAC Conference on Programmable Devices and Embedded Systems (PDeS 2015), Krakow, Poland, May 13-15, 2015.
  • Sandeep Raj and Kailash Chandra Ray, “A comparative study of multivariate approach with neural networks and Support Vector Machine for arrhythmia classification“,IEEE Int. conf. on energy, power and environment (IEEE-ICEPE-2015), NIT Shillong, India, 12th-13th June 2015.
  • K. K. Soundra Pandian, S. Pal and Kailash Chandra Ray, “Design and Implementation of Dynamic key based stream cipher for cryptographic processor”, IEEE Int. Conf. on Signal processing , Communication and Networking (IEEE-ICSCN-2015), Chennai, India, 26th-28th Mar. 2015.
  • Rakesh Palisetty,  Vibhooti Kumar Sinha,  Saugata Mallick, and K. C. Ray, "FPGA prototyping of energy dispersal and improved error efficiency techniques for DVB-satellite standard",  IEEE Int. Conf. VLSI Systems, Architecture, Technology and Applications (VLSI-SATA), Page(s): 1 -5 , January 2015 (DOI: 10.1109/VLSI-SATA.2015.7050493). 
  • K. C. Ray and A. S. Dhar, "Parallel architecture for real time computation of discrete Mellin transform", IEEE Int. Conf. Emerging Technology Trends in Electronics, Communication and Networking (ET2ECN), Page(s): 1-3, December 2014(DOI: 10.1109/ET2ECN.2014.7044949).
  • S. Pal, K. K. Soundra Pandian, and K. C. Ray, " FPGA implementation of stream cipher using Toeplitz Hash function", IEEE Int. Conf. Advances in Computing, Communications and Informatics (IEEE-ICACCI 2014), Page(s): 1834 - 1838,September 2014 (DOI:  10.1109/ICACCI.2014.6968290).
  • Abdul Rawoof, Kulesh Kumar and K. C. Ray, "ARM Based Implementation of Text-to-Speech (TTS) for Real Time Embedded System", 5th Int. IEEE Conf. Signal and Image Processing (IEEE-ICSIP-2014), Page(s): 192 - 196, January 2014. (DOI: 10.1109/ICSIP.2014.36).
  • Ramu Endluri,  Mohith Kathait,  K.C. Ray, "Face recognition using PCA on FPGA based embedded platform", Proc. Int. Conf. Control, Automation, Robotics and Embedded Systems IEEE-CARE) December 2013. (DOI: 10.1109/CARE.2013.6733778)
  • Kshitij,  Shaik Abdul Rawoof, K.C. Ray, "Implementation of Mellin transform using FPGA based embedded system platform", 2nd Int. Conf. Power, Control and Embedded Systems (IEEE-ICPCES-2012), December 2012 (DOI: 10.1109/ICPCES.2012.6508091).
  • V. Gautam, K. C. Ray, P. Haddow, “Hardware efficient design of Variable Length FFT Processor”, Proc. IEEE 14th Int. Sympo. Design and Diagnostics of Electronic Circuits & Systems (IEEE-DDECS 2011), Cottbus, Germany, pp 309-312, Apr 2011.
  • M. V. N. V. Prasad, K. C Ray and A. S. Dhar, "FPGA implementation of Discrete Fractional Fourier Transform", Proc. Int. Conf. Signal Processing and Communication (IEEE-SPCOM), IISc Bangalore, pp.1-5, 18-21 July 2010.
  • K. C. Ray, R. Shukla and A. S. Dhar, "CORDIC-based VLSI Architecture for implementing Log-Polar Transformation for real time applications", Int. Conf. Computing, Commun. And Networking Technologies (IEEE-ICCCNT 2010), Karur, India, pp.1-4, July 2010.
  • R. Chand, P. Tripathy, A. Mathur and K.C. Ray, "FPGA implementation of fast FIR low pass filter for EMG removal from ECG signal", Proc. Int. Conf. Power, Control and Embedded Systems (IEEE-ICPCES-2010), MNNIT, Allahabad, India, Nov. 2010. (Digital Object Identifier: 10.1109/ICPCES.2010.5698652)
  • P. Tripathy, R. Chand, A. Mathur and K.C. Ray, "FPGA implementation of running DFT for selective harmonics analysis ", Proc. Int. Conf. Power, Control and Embedded Systems (IEEE-ICPCES-2010), MNNIT, Allahabad, India, Nov. 2010. (Digital Object Identifier: 10.1109/ICPCES.2010.5698718)
  • A. K. Khare and K. C. Ray, "Design and VLSI implementation of 128-point single data path FFT processor for OFDM and UWB applications", Proc. Int. Conf. Innovative Tech. (ICIT 09), Bahadurgarh, India, Vol.1, pp. 254-257, Jun. 2009.
  • K. C. Ray, R. Teja, A. S. Dhar and I. Chakraborty, "Fast and flexible VLSI architecture for one dimensional median filter., Proc. Int. Conf. RF Signal Processing Systems, Vijayawada, India, pp.75-80, 1st-2nd Feb. 2008.
  • R. Teja, K. C. Ray, I. Chakraborty and A.S. Dhar, "High throughput VLSI architecture for one dimensional digital median filter", Proc. Int. Conf. Signal Process. Commun. Networking (IEEE-ICSCN 08), Chennai, India, pp.426-431, 4-6th Jan. 2008.
  • K. C. Ray and A. S. Dhar, "ASIC architecture for implementing Blackman windowing for real time spectral analysis", Proc. Int. Conf. Signal Processing, Commun. Networking (IEEE-ICSCN 07), Chennai, India, pp.388-391, 22-24th Feb. 2007.
  • K. C. Ray and A. S. Dhar, "CORDIC based VLSI architecture for Hanning and Hamming windowing for real time spectral analysis", Proc. Int. Conf. Comput. Devices Commun., (CODEC06), Kolkata, India, pp.154-157, 18-20th Dec. 2006.